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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
2.3
Memory Map Summary
The device provides 16M bytes of total memory space composed of on-chip RAM, on-chip ROM, and
external memory space supporting a variety of memory types. The on-chip, dual-access RAM allows two
accesses to a given block during the same cycle. There are 8 blocks of 8K bytes of dual-access RAM.
The on-chip, single-access RAM allows one access to a given block per cycle. In addition, there are 32
blocks of 8K bytes of single-access RAM.
The remainder of the memory map is divided into five external spaces, and on-chip ROM. Each external
space has a chip select decode signal (called EM_CS0, EM_CS[2:5]) that indicates an access to the
selected space. The external memory interface (EMIF) supports access to asynchronous memories such
as SRAM, NAND, or NOR and Flash, and mobile single data rate (mSDR) and single data rate (SDR)
SDRAM.
The DSP memory is accessible by different master modules within the DSP, including the C55x CPU, the
four DMA controllers, LCD, and the CDMA of USB (see Figure 2-1 ).
CPU BYTE
DMA/USB/LCD
ADDRESS (A)
BYTE ADDRESS (A)
MEMORY BLOCKS
BLOCK SIZE
000000h
0000C0h
010000h
050000h
0001 0000h
0001 00C0h
0009 0000h
0100 0000h
MMR (Reserved)
(D)
DARAM
SARAM
(B)
64K Minus 192 Bytes
256K Bytes
800000h
0200 0000h
External-CS0 Space
(C)(E)
8M Minus 320K Bytes SDRAM/mSDRAM
C00000h
E00000h
F00000h
FE0000h
0300 0000h
0400 0000h
0500 0000h
050E 0000h
External-CS2 Space
External-CS3 Space
External-CS4 Space
External-CS5 Space
(C)
(C)
(C)
(C)
4M Bytes Asynchronous
2M Bytes Asynchronous
1M Bytes Asynchronous
1M Minus 128K Bytes Asynchronous
FFFFFFh
050F FFFFh
ROM
(if MPNMC=0)
Reserved
(i f MPNMC=1)
Unmapped (if MPNMC=1)
128K Bytes ROM (if MPNMC=0)
A.
B.
C.
D.
E.
Address shown represents the first byte address in each block.
The first 192 bytes are reserved for memory-mapped registers (MMRs).
Reading/Writing to/from unmapped returns zeros.
The USB and LCD controllers do not have access to DARAM.
The CS0 space can be accessed by CS0 only or by CS0 and CS1.
Figure 2-1. Memory Map Summary
Copyright ? 2010–2013, Texas Instruments Incorporated
Product Folder Links: TMS320C5515
Device Overview
13
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